1. Field of the Invention
The present invention relates to a technology for reading data, based on which an error correcting code is to be generated, from a storage device.
2. Description of the Related Art
With the progress in the miniaturization in the field of semiconductor technologies, smaller storage elements are being used in random access memories (RAMs) of central processing units (CPUs). Such a small storage element, however, causes accidental inversion of data stored in the RAM. In an internal circuit of the RAM, a margin of a timing adjustment value is reduced to increase the operating frequency, which results in the RAM circuit being susceptible to fluctuation in voltage and temperature.
As a result, failure modes unanticipated heretofore occur. Failure modes include, for example, intermittent failure in the RAM cells due to alpha rays, resulting in damage to the data in the RAM, or intermittent write failure where the value of the RAM cells are not properly updated, or intermittent read failure caused by write recovery failure where the correct value is not read even if the correct value is stored in the RAM.
FIGS. 7 and 8 are schematic diagrams for explaining the write recovery failure in the RAM circuit. FIG. 7 is an example of the RAM circuit; and FIG. 8 is graphs of waveforms in the RAM circuit. The write recovery failure is a phenomenon in which if the data written to the RAM (for example, static RAM (SRAM)) is read immediately after it is written, the data remains in the bit line, which decreases the read margin of the next cycle. Write recovery failure occurs when, for example, the SRAM is operated at an operating cycle greater than the set value or when individual difference among the transistors is beyond what the designer anticipated.
To prevent the data from remaining in the bit line after being written, the SRAM circuit is designed in such a way that the bit line is shorted to source voltage Vdd within a specified time using precharged transistors (TrA, TrB, and TrC shown in FIG. 7). In other words, when writing the data, depending on the write data, the voltage of one bit line (the bit line represented by Bit in the waveform shown in FIG. 8) of the bit line pair (Bit and /Bit shown in FIG. 7) is lowered to a low level, and after writing is completed, the data is cleared away by shorting the bit line pair (Bit and /Bit) to the source voltage Vdd by the time the next read cycle starts.
However, if the precharged transistor is weak, the voltage at the bit line shows a dash-line waveform of a third graph from the top shown in FIG. 8. In other words, the voltage does not come up to the source voltage Vdd even after the next read cycle starts, leaving a difference in the potential in the bit lines. If reading starts in this state, the amplitude picked up by the original sense amplifier decreases, resulting in a read error or intermittent read failure.
Addressing the failure modes, Japanese Patent Application Laid-open No. H9-134314 discloses a mode in which the data stored in the RAM is directly transferred to an executing device (direct transfer mode) or after detecting and correcting error in the data (correction transfer mode). In other words, the data that needs to be quickly transferred to the computer device is transferred by the direct transfer mode and the data that does not need to be quickly transferred is transferred by the correction transfer mode, thus providing an effective solution to the failure modes occurring when reading from the RAM.
However, the conventional technology described above does not address the intermittent read failure caused by write recovery failure.
Intermittent read failure refers to read error occurring haphazardly even if correct data is stored in the RAM. Therefore, the same data read accurately the first time may fail to be read the second time.
If intermittent read failure occurs during storing operation in an operand cache of the CPU, even one-bit error is treated as uncorrectable error.
When the intermittent read failure is caused by write recovery failure, there is no use checking for error, far less correcting it, as the data stored in the RAM is correct in the first place.